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tc7mh123,221afk 2001-09-12 1 toshiba cmos digital integrated circuit silicon monolithic TC7MH123AFK,tc7mh221afk dual monostable multivibrator TC7MH123AFK retriggerable tc7mh221afk non-retriggerable the TC7MH123AFK, tc7mh221afk are advanced high speed cmos monostable multivibrators fabricated with silicon gate c 2 mos technology. there are two trigger inputs, a input (negative edge), and b input (positive edge). these inputs are valid for a slow rise/fall time signal (t r = t f = 1 s) as they are schmitt trigger inputs. this device may also be triggered by using clr input (positive edge). after triggering, the output stays in a monostable state for a time period determined by the external resistor and capacitor (rx, cx). a low level at the clr input breaks this state. limits for cx and rx are: external capacitor, cx ......... no limit external resistor, rx............ v cc = 2.0 v more than 5 k ? v cc = 3.0 v more than 1 k ? an input protection circuit ensures that 0 to 7 v can be applied to the input pins without regard to the supply voltage. this device can be used to interface 5 v to 3 v systems and two supply systems such as battery back up. this circuit prevents device destruction due to mismatched supply and input voltages. features high speed: t pd = 8.1 ns (typ.) (v cc = 5 v) low power dissipation: standby state i cc = 4 a (max) (ta = 25c) active state i cc = 600 a (max) (v cc = 5.0 v) high noise immunity: v nih = v nil = 28% v cc (min) power down protection is equipped with all inputs. balanced propagation delays: t plh t phl wide operating voltage range: v cc (opr) = 2~5.5 v pin and function compatible with 74hc123a/221a weight: 0.02 g (typ.)
tc7mh123,221afk 2001-09-12 2 pin assignment (top view) note: when using a single circuit only, please set clr to l, keep rx/cx ? q ? q open and set other pins to either h or l. iec logic symbol truth table inputs outputs a b clr q q note h h output enable x l h l h inhibit h x h l h inhibit l h output enable l h output enable x x l l h reset x: don?t care a 1 1 2 3 4 5 6 7 1b clr 1 q 1 2q 2cx 2rx/cx 8 gnd 1cx 14 1q q 2 clr 2 2b a 2 13 12 11 10 9 15 1rx/cx 16 v cc & r cx rx/cx TC7MH123AFK ( 1 ) ( 2 ) ( 3 ) ( 14 ) ( 15 ) ( 13 ) ( 4 ) ( 9 ) ( 10 ) ( 11 ) ( 6 ) ( 7 ) ( 5 ) ( 12 ) 2rx/c x 2c x clr 2 2b a 2 1rx/c x clr 1 1b a 1 1c x 1q q 1 2q q 2 & r cx rx/cx tc7mh221afk ( 1 ) ( 2 ) ( 3 ) ( 14 ) ( 15 ) ( 13 ) ( 4 ) ( 9 ) ( 10 ) ( 11 ) ( 6 ) ( 7 ) ( 5 ) ( 12 ) 2rx/c x 2c x clr 2 2b a 2 1rx/c x clr 1 1b a 1 1c x 1q q 1 2q q 2 1
tc7mh123,221afk 2001-09-12 3 block diagram note1: cx, rx, dx are external capacitor, resistor, and diode, respectively. note2: external clamping diode, dx; the external capacitor is charged to v cc level in the wait state, i.e. when no trigger is applied. if the supply voltage is turned off, cx is discharges mainly through the internal (parasitic) diode. if cx is sufficiently large and v cc drops rapidly, there will be some possibility of damaging the ic through in rush current or latch-up. if the capacitance of the supply voltage filter is large enough and v cc drops slowly, the in rush current is automatically limited and damage to the ic is avoided. the maximum value of forward current through the parasitic diode is 20 ma. in the case of a large cx, the limit of fall time of the supply voltage is determined as follows: t f (v cc 0.7) ? cx/20 ma (t f is the time between the supply voltage turn off and the supply voltage reaching 0.4 v cc ) in the even a system does not satisfy the above condition, an external clamping diode (dx) is needed to protect the ic from rush current. d x r x 15 14 clr 13 4 q q 1 2 a b 3 v cc cx rx/cx c x d x r x 7 6 clr 5 12 q 9 10 a b 11 v cc cx rx/cx c x q
tc7mh123,221afk 2001-09-12 4 system diagram TC7MH123AFK timing chart TC7MH123AFK t w out t w out t rr t w out t rr v ih v il v ih v il v ih v il v ol v oh v ol a b clr r x /c x q q v cc v ref h v ref l gnd v oh q q v ref v cc q p v ref l c1 c2 h clr r x /c x c x a b f/f q n r d q ck q v cc
tc7mh123,221afk 2001-09-12 5 system diagram tc7mh221afk timing chart tc7mh221afk t w out t w out v ih v il v ih v il v ih v il v ol v oh v ol a b clr r x /c x q q v cc v ref h v ref l gnd v oh t w out q q v ref v cc q p v ref l c1 c2 h clr r x /c x c x a b f/f q n r d q ck q
tc7mh123,221afk 2001-09-12 6 functional description (1) stand-by state the external capacitor (cx) is fully charged to v cc in the stand-by state. that means, before triggering, the q p and q n transistors which are connected to the rx/cx node are in the off state. two comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off. the total supply current is only leakage current. (2) trigger operation trigger operation is effective in any of the following three cases. a input is low, and the b input has a rising signal b input is high, and the a input has a falling signal a input is low and the b input is high, and the clr input has a rising signal after a trigger becomes effective, comparators c1 and c2 start operating, and q n is turned on. the external capacitor discharges through q n . the voltage level at the rx/cx node drops. if the rx/cx voltage level falls to the internal reference voltage vref l, the output of c1 becomes low. the flip-flop is then reset and q n turns off. at that moment c1 stops but c2 continues operating. after q n turns off, the voltage at the rx/cx node starts rising at a rate determined by the time constant of external capacitor cx and resistor rx. upon triggering, output q becomes high, following some delay time of the internal f/f and gates. it stays high even if the voltage of rx/cx changes from falling to rising. when rx/cx reaches the internal reference voltage vref h, the output of c2 becomes low, the output q goes low and c2 stops its operation. that means, after triggering, when the voltage level of the rx/cx node reaches vref h, the ic returns to its monostable state. with large values of cx and rx, and ignoring the discharge time of the capacitor and internal delays of the ic, the width of the output pulse, t w (out), is as follows: t w (out) 1.0 cx rx (3) retrigger operation (TC7MH123AFK) when a new trigger is applied to either input a or b while in the monostable state, it is effective only if the ic is charging cx. the voltage level of the rx/cx node then falls to vref l level again. therefore the q output stays high if the next trigger comes in before the time period set by cx and rx. if the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle, it will have no effect. the minimum time for a trigger to be effective 2nd trigger, t rr (min), depends on v cc and cx. (4) reset operation in normal operation, the clr input is held high. if clr is low, a trigger has no effect because the q output is held low and the trigger control f/f is reset. also, q p turns on and cx is charged rapidly to v cc . this means if clr is set low, the ic goes into a wait state.
tc7mh123,221afk 2001-09-12 7 maximum ratings (ta 25c) characteristics symbol rating unit supply voltage range v cc 0.5~7.0 v dc input voltage v in 0.5~7.0 v dc output voltage v out 0.5~v cc 0.5 v input diode current i ik 20 ma output diode current i ok 20 ma dc output current i out 25 ma dc v cc /ground current i cc 50 ma power dissipation p d 180 mw storage temperature t stg 65~150 c recommended operating conditions characteristics symbol rating unit supply voltage v cc 2.0~5.5 v input voltage v in 0~5.5 v output voltage v out 0~v cc v operating temperature t opr 40~85 c 0~100 (v cc 3.3 0.3 v) input rise and fall time ( clr only) dt/dv 0~20 (v cc 5 0.5 v) ns/v external capacitor cx no limitation (note3) f 5 k (v cc 2.0 v) (note3) external resistor rx 1 k (v cc 3.0 v) (note3) note3: the maximum allowable values of cx and rx are a function of leakage of capacitor of cx, the leakage of tc7mh123a/221a, and leakage due to board layout and surface resistance. susceptibility to externally induced noise signals may occur for rx 1 m .
tc7mh123,221afk 2001-09-12 8 electrical characteristics dc characteristics ta 25c ta 40~85c characteristics symbol test condition v cc (v) min typ. max min max unit 2.0 1.50 1.50 high level v ih 3.0~5.5 v cc 0.7 v cc 0.7 2.0 0.50 0.50 input voltage low level v il 3.0~5.5 v cc 0.3 v cc 0.3 v 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 i oh 50
a 4.5 4.4 4.5 4.4 i oh 4 ma 3.0 2.58 2.48 high level v oh v in v ih or v il i oh 8 ma 4.5 3.94 3.80 2.0 0 0.1 0.1 3.0 0 0.1 0.1 i ol 50
a 4.5 0 0.1 0.1 i ol 4 ma 3.0 0.36 0.44 output voltage low level v ol v in v ih or v il i ol 8 ma 4.5 0.36 0.44 v input leakage current i in v in 5.5 v or gnd 0~5.5 0.1 1.0
a rx/cx terminal off-state current i in v in v cc or gnd 5.5 0.25 2.50
a quiescent supply current i cc v in v cc or gnd 5.5 4.0 40.0
a 3.0 160 250 280 4.5 380 500 650 active-state supply current (note4) i cc v in v cc or gnd rx/cx 0.5 v cc 5.5 560 750 975
a note4: per circuit timing requirements (input: t r t f 3 ns) ta 25c ta 40~85c characteristics symbol test condition v cc (v) typ. limit limit unit 3.3 0.3 5.0 5.0 minimum pulse width t w (l) t w (h) 5.0 0.5 5.0 5.0 ns 3.3 0.3 5.0 5.0 minimum clear width ( clr ) t w (l) 5.0 0.5 5.0 5.0 ns 3.3 0.3 60 rx 1 k cx 100 pf 5.0 0.5 39 ns 3.3 0.3 1.5 minimum retrigger time (note5) t rr rx 1 k cx 0.01
f 5.0 0.5 1.2
s note5: for TC7MH123AFK only
tc7mh123,221afk 2001-09-12 9 ac characteristics (input: t r t f 3 ns) ta 25c ta 40~85c characteristics symbol test condition v cc (v) c l (pf) min typ. max min max unit 15 13.4 20.6 1.0 24.0 3.3 0.3 50 15.9 24.1 1.0 27.5 15 8.1 12.0 1.0 14.0 propagation delay time (a, b-q, q ) t plh t phl 5.0 0.5 50 9.6 14.0 1.0 16.0 ns 15 14.5 22.4 1.0 26.0 3.3 0.3 50 17.0 25.9 1.0 29.5 15 8.7 12.9 1.0 15.0 propagation delay time ( clr trigger-q, q ) t plh t phl 5.0 0.5 50 10.2 14.9 1.0 17.0 ns 15 10.3 15.8 1.0 18.5 3.3 0.3 50 12.8 19.3 1.0 22.0 15 6.3 9.4 1.0 11.0 propagation delay time ( clr -q, q ) t plh t phl 5.0 0.5 50 7.8 11.4 1.0 13.0 ns 3.3 0.3 50 160 240 300 cx 28 pf rx 2 k 5.0 0.5 50 133 200 240 ns 3.3 0.3 50 90 100 110 90 110 cx 0.01
f rx 10 k 5.0 0.5 50 90 100 110 90 110
s 3.3 0.3 50 0.9 1.0 1.1 0.9 1.1 output pulse width t wout cx 0.1
f rx 10 k 5.0 0.5 50 0.9 1.0 1.1 0.9 1.1 ms output pulse width error between circuits (in same package) t wout 50 1 % input capacitance c in 4 10 10 pf power dissipation capacitance c pd (note6) 73 pf note6: c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. average operating current can be obtained by the equation: i cc (opr) c pd ? v cc ? f in i cc ? ? duty/100 i cc /2 (per circuit) (i cc ?: active supply current) (duty: %)
tc7mh123,221afk 2001-09-12 10 input equivalent circuit input supply voltage v cc (v) external capacitor cx (pf) t wout ? c x characteristics (typ.) output pulse width t wout ( s) 10 2 10 3 10 4 10 1 v cc 4.5 v c l 50 pf 10 3 rx 1 m rx 100 k rx 10 k rx 1 k 10 1 10 2 minimum retrigger time t rr ( s) supply voltage v cc (v) t rr ? v cc characteristics (typ.) (TC7MH123AFK) 10 0.01 0 ta 25 c cx 1000 pf cx 0.01 f cx 100 pf 123 4 5 6 1 0.1 output pulse width constant k ? supply voltage (typ.) output pulse width constant k (external resistor (rx) 10 k : t wout k ? cx ? rx) 2 1.2 1.1 1.0 3 4 5 6 cx 1000 pf cx 0.01 f cx 1 f, cx 0.1 f
tc7mh123,221afk 2001-09-12 11 package dimensions weight: 0.02 g (typ.)
tc7mh123,221afk 2001-09-12 12 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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